Saturday, 14 November 2015


Finishing the Chip

Now a gate is add to the silicon. A gate is a thin layer of silicon oxide which acts as an insulator. The first part is put between the source and the drain. This is accomplished by chemical vapour deposition (CVD). CVD is done by filling a furnace with gases so a chemical reaction takes place on the surface of the silicon. Next a layer of conductive silicon is put over the silicon oxide layer. CVD is use for this as well.
Billions of MOSFETs put on the wafer but now they need to be connected. Fist we must insulate the silicon with a layer of silicon dioxide by CVD. Now that the surface is insulated can't make connection to the Source, Drain or Gate. To remake the connection they use a method called double damascene. Need to make tungsten connecting pin and copper interconnect. Hydrofluoric acid etches holes into the silicon dioxide through photoresist. Next the interconnection tracks are etched in. A top layer of copper is electroplated on. It fills the holes to make connections in the MOSFETs. The pins through the insulating layer are called vias. Now the top layer of copper is removed using chemical mechanical polishing. The pin pins in the tracks are left. A final insulating layer of silicon dioxide is connected using the vias.
The wafer has hundreds of chip on it and they have to be checked if they are working or not.

This is done with a wafer probe. Uses pins that touch the contact of the chip and pass electrical signals. Sometimes if part of the chip does not work it is sold as a lower end chip.
Finally the chips are cut out and pack and sent off.
I referenced

Intel Museum website

Tech Radar


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